1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method of forming a copper metal interconnection of a semiconductor device using a damascene process.
2. Description of the Related Art
In a semiconductor manufacturing process a front end of the line (FEOL) process may involve forming a transistor on a silicon substrate, whereas a back end of the line (BEOL) process may involve forming metal interconnections. The interconnection technology refers to a process of electrically connecting transistors to each other in order to realize power supply and signal transmission paths that constitute an integrated circuit on a silicon substrate.
In such interconnection technology, copper (Cu), having high electro-migration (EM) is widely used.
However, since copper (Cu) is not easily etched but is oxidized during the process, a copper metal interconnection is formed through a dual damascene process unlike a common metal process.
In particular, in the dual damascene process, after forming a via and a trench in an interlayer dielectric layer, copper is buried in a via or a trench using an electro-chemical plating (ECP) method and planarization is performed by a chemical mechanical polishing (CMP) process to form a copper interconnection.
Furthermore, in the dual damascene process, a damascene pattern including the via and the trench are formed in the interlayer dielectric layer.
Since it is possible to reduce a step difference between metal interconnections by the dual damascene process, it is possible to easily perform sequential processes.
A conventional method for forming the damascene pattern consists of a method of forming a via followed by a method of forming a trench or vice versa.
No matter which method is used, various steps involving photolithography and etching processes which must be performed, increases in comparison with a common metal interconnection process.
The most widely used method is the method of first forming the via. Referring to FIGS. 1A to 1E, a conventional damascene pattern forming method will be briefly described.
Referring to FIG. 1A, a barrier insulating layer 11 and an interlayer dielectric layer 12 are sequentially deposited on a substrate 10 or a lower metal interconnection (not shown). As illustrated in FIG. 1B, a via hole 14 is formed in inter layer dielectric layer 12 using a photolithography process and an etching process. Barrier insulating layer 11 under interlayer dielectric layer 12 is used as an etch stop layer.
As illustrated in FIG. 1C, after applying an anti-reflective material 14a on the entire surface of interlayer dielectric layer 12, anti-reflective material 14a formed on interlayer dielectric layer 12 is removed with anti-reflective material 14a left only in via hole 14. As illustrated in FIG. 1D, a trench 15 is formed in interlayer dielectric layer 12 using a photolithography process and a etching process. While interlayer dielectric layer 12 is etched, a part of anti-reflective material 14a formed in via hole 14 is removed.
Illustrated in FIG. 1E, anti-reflective material (14a of FIG. 1D) that resides in via hole 14 is removed and a part of barrier insulating layer 11 exposed by via hole 14 is removed. The barrier metal layer is deposited on the entire surface of the resultant material and the copper is buried in via hole 14 and trench 15 using an ECP method. Finally, planarization is performed to the surface of the interlayer dielectric layer using the CMP process to complete the copper metal interconnection.
In the above-described dual damascene process, the method of first forming the via hole, and then forming the trench is performed. The anti-reflective material is buried in the via hole and a trench etching process is performed. The buried anti-reflective material is removed through an ashing process. However, a by-product can be formed in the trench etching process in accordance with etching selectivity with respect to the anti-reflective material. As illustrated in FIG. 1D, the by-product generated by the trench etching process forms a fence 14b on the via hole. Thus fence 14b resides without being removed in the sequential ashing process. When fence 14b is not completely removed, the barrier metal layer formed in order to prevent the copper from being diffused is not uniformly deposited around the via hole. Therefore, in the region where fence 14b is formed, the diffusion path of the copper can be formed. Also, due to fence 14b, defects such as voids may be caused in the copper interconnection formed by an ECP method.